1. Field of the Invention
The invention relates to the general field of integrated circuit packaging, more particularly to ball grid arrays and how to attach them to printed circuit boards with minimum introduction of mechanical stress.
2. Description of the Prior Art
The wiring used for interconnection within a semiconductor chip is extremely fine, being of the order of a few microns, or less, in width. The abilty to form such wires has made possible chips containing hundreds of thousands, and more, interconnected components. At some point, however, contact must be made between the chips and the outside world where working to such small tolerances is not possible.
The most widely used medium for connecting chips to one another and/or the outside world is the printed circuit board (PCB). The term PCB is used here in a generic sense encompassing all types of printed circuit wiring, including what are known in the industry as cards and boards. The wiring on a PCB is much coarser than on a chip being typically measured in millimeters. It is not practical to connect chip wiring directly to PCB wiring. Therefore, an intermediate structure, capable of handling both ends of this wire-width spectrum, is needed.
An example of such a structure is a ball grid array (BGA), an example of which is shown in FIG. 1, in schematic cross-section. Semiconductor die 1 has been attached, face up, to the top surface of insulating substrate 2 comprised of ceramic, plastic, or glass, etc. Said top surface of the BGA is imprinted with fine wiring 9 that can be connected to the I/O (input-output) pads 10 of said die while the other surface is imprinted with relatively coarse wiring (not shown) with its own set of I/O pads (such as 6) in the form of solder balls or joints. The latter are distributed over an area that is substantially larger than the area occupied by the corresponding I/O pads on the chip, thereby making them more compatible with printed circuit wiring.
Multiple layers of wiring, embedded within the BGA substrate, serve to route signals from the various I/O pads on the chip to the appropriate solder joints on the other surface of the substrate. Vias directly below the die, such as 5, are generally used to transfer heat or to serve as ground connectors while other vias, such as 3, as generally used to carry signals. Solder mask 7 is located over those portions of the lower surface not occupied by the solder balls and serves to protect any wiring on that surface from contact with any excess solder exuded by the solder balls during melting.
The method of connection, from die to BGA, shown in FIG. 1 is but one of several that are in general use. For example, in flip chip technology the die is mounted face down and contact to the BGA is made through solder balls, rather than wire bonds such as 4 in FIG. 1. Yet another commonly used interconnection technique is Tape Automated Bonding, similar to wire bonding except that the wire bonds are preprinted on special tape and then removed (by virtue of being transferred to BGA and die) in a single operation. Also shown in FIG. 1 is a layer of encapsulating resin 8 which serves to protect the die from damage and/or contamination during its operating life.
It is not unusual to place more than one chip on a single BGA. In that case, connections between chips may be made via the aforementioned embedded wiring in addition to the rerouting of I/O locations previously discussed. It is also possible to locate discrete components, such as capacitors, on the BGA and connect them to the chips as well. The wiring density within such multi- chip-modules (MCMs) is greater than within the boards onto which they will be mounted, so MCMs can be used to achieve an overall reduction in package size relative to single chip modules.
Regardless of how many chips are located on a given BGA, the fully assembled package, comprising the unpackaged chip (or die), BGA, and PCB is subject to a substantial amount of internal mechanical stress as a consequence of thermal mismatch between its various parts. Furthermore, when the BGA is being bonded to the PCB by heating the assemblage in order to melt the solder joints, the weight of the BGA can cause significant distortion of the molten joints causing them to subsequently freeze in a barrel-like shape that has much built-in stress. This is generally not as severe a problem for the semiconductor die, even if it is attached through flip chip technology (i.e. solder joints connecting die to BGA), since it is much lighter than the BGA, so the surface tension of the molten solder joints, which pulls the molten solder into an hour-glass shape, dominates over the compression effect.
Another source of built-in stress can be introduced into the package if, as is commonly done, the semiconductor die is encapsulated in a protective plastic resin. Additionally, during its operating lifetime, the package will repeatedly be cycled over a relatively wide range of temperatures. This, in combination with the aforementioned built-in internal stresses, can lead to mechanical failure of the package.
A number of approaches to mitigating these various stress effects have already been proposed. For example, Christie et al. (U.S. Pat. No. 5,250,848 Oct. 5 1993) has disclosed the use of certain encapsulants to absorb the stress while Melton et al. (U.S. Pat. No. 5,233,504 Aug. 3 1993) and Okumura (U.S. Pat. No. 4,807,021 Feb 21 1989) use balls made of a relatively high melting point material that have been coated with a layer of soft material. During package assembly, the balls do not melt so the afore-mentioned collapse into the barrel shape does not occur. After assembly, the soft outer layer acts as a buffer to absorb some of the built-in or subsequently generated stress.
Blanton (U.S. Pat. No. 5,220,200 Jun. 15 1993) prevents the solder ball collapse (thus avoiding ending up with barrel shaped solder joints) by providing pillars that support the BGA during melting. Said pillars are built up out of metal paste laid down as part of several paste screening steps.
As will be shown below, none of these inventions anticipates the present invention.